The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of checking whether a plurality of banks are overlappingly operated.
FIG. 1 is a circuit diagram of a bank active signal generating circuit in a conventional semiconductor memory device. Referring to FIG. 1, the bank active signal generating circuit is provided as many as banks of the semiconductor memory device, but only a circuit for generating a bank active signal BANK_ACT<0> of a bank 0. An active signal ACT is enabled when an active command is applied to the semiconductor memory device, without discriminating banks, and a bank address BANK<0> is enabled when a bank 0 is selected.
The bank active signal BANK_ACT<0> of the bank 0 is enabled when the active signal ACT and the bank address BANK<0> are enabled. When the active signal ACT is disabled, the bank active signal BANK_ACT<0> of the bank 0 is disabled. That is, the bank 0 is activated when the external active command is applied and the bank 0 is selected by the address. The banks 1, 2 and 3 are activated in the same manner as the bank 0.
In an active operation of the semiconductor memory device, a normal operation can be achieved when only a bank selected by a bank address is activated. However, several banks may be erroneously activated at the same time due to mismatch of internal timing margins or glitches.
Data error occurs when the banks are overlappingly activated. A constant amount of power to be supplied to one bank is supplied to several banks, leading to degradation of bank performance.
However, since such a problem occurs inside the semiconductor memory device, it is impossible to detect whether the banks are overlappingly activated. That is, it is impossible to intuitively find whether the problem occurs due to the overlap activation of the banks or other factors.